用VHDL語言描述壹個分頻器，將1000HZ分頻成1HZ,
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ffpin is
port (clk1k:in std_logic;
ft:out std_logic);
end ffpin;
architecture a of ffpin is
signal fm:std_logic;
begin
process(clk1k)
variable num:integer range 0 to 1000;
begin
if clk1k'event and clk1k='1' then
if num<500 then
num:=num+1;
else
num:=1;
fm<=not fm;
end if ;
end if;
ft<=fm;
end process;
end a;
這個程序輸入為1kHz時，輸出為1Hz